The present invention is applicable to semiconductor memories, especially dynamic random access memory (DRAM). In particular, the present invention relates to a method and apparatus for controlling refresh operations in a semiconductor memory such that the data retention time in standby mode is made""significantly longer than the data retention time in a normal operating mode.
Due to charge leakage, data stored in a DRAM cell must be refreshed periodically. The time elapsed from the time that data is written to a DRAM cell to the time that the data is on the threshold of being corrupted due to charge leakage is referred to as the data retention time of the memory. The longer the data retention time, the less frequently the memory cell needs to be refreshed. Each refresh operation in a DRAM device consumes power. Therefore the longer the data retention time, the lower the required refresh power.
Refresh (or data retention) power is required even when the memory is not being accessed (i.e., when the memory is in a standby mode). Standby mode is defined as a mode in which the memory is not accessed, and some or all of the data stored in the memory is retained. In a power critical application, such as a cell phone, the majority of the power required in standby mode is consumed by performing refresh operations for the DRAM memory. In such an application, it is important to keep the refresh power as low as possible.
A traditional DRAM cell consists of one transistor and one capacitor. Data is stored in a cell in the form of charges in the capacitor. In general, one DRAM cell can store one bit of binary data.
FIG. 1 is a circuit diagram of a traditional DRAM array 100, in which a plurality of DRAM cells are arranged in rows and columns. DRAM array 100 includes word lines WL0-WL8 and bit lines BLI, BLI#, BLI+1 and BLI+1#. DRAM array 100 also includes 18 DRAM cells, including DRAM cells 101-104. Each of the DRAM cells includes a capacitor element (represented by a large open square), and an access transistor, which couples the capacitor element to a bit line. The connections between the bit lines and the access transistor drain regions are shown as boxes containing an xe2x80x9cXxe2x80x9d. For example, DRAM memory cell 101 includes capacitor element 111 and access transistor 112.
Within array 100, a column includes a bit-line pair and the associated memory cells. Thus, bit lines BLI and BLI# and the DRAM cells coupled to these bit lines form one column of array 100. Bit lines BLI+1 and BLI+1# and the DRAM cells coupled to these bit lines form another column of array 100. Each memory cell is only coupled to one of the two bit lines in the column. A row consists one cell from each column. Thus, the first row consists of DRAM cells 102 and 104 (which are controlled by word line WL0), and the second row consists of the DRAM cells 101 and 103 (which are controlled by word line WL1). The configuration of memory array 100 is a well-known folded bit-line architecture.
To perform a memory access, all of the bit lines BLI, BLI#, BLI+1 and BLI+1# are pre-charged to a fixed voltage. For example, the bit lines can be charged to a voltage equal to half of a supply voltage (VDD/2). One of word lines WL0-WL8 is then turned on, thereby connecting one DRAM cell from each column to one of the two bit lines in the column. For example, word line WL1 can be turned on, thereby coupling DRAM cell 101 to bit line BLI (and DRAM cell 103 to bit line BLI+1). The charge stored in charge storage element 111 of DRAM cell 101 is shared with bit line BLI, and thereby alters the voltage on this bit line. However, the complimentary bit line BLI# of the same column remains floating, such that the voltage on this complementary bit line is not directly changed by any DRAM cell charge. Each bit line pair is connected to a sense amplifier, which amplifies the signal difference between the complimentary bit lines. The amplified signals in the bit-line pairs are multiplexed to the data lines through column switches. The difference in the voltage (xcex94V) between the complimentary bit lines, before the sense amplifier is turned on, has to overcome any offset in the sense amplifier and any noise that may exist during sensing in order for the data to be sensed accurately. The voltage difference xcex94V is dependent mainly on the charge stored in the capacitor element. This charge leaks over time. The longer the refresh period, the greater the charge leakage, and the smaller the voltage difference xcex94V. The above-described operating mode of DRAM array is commonly referred to as single-cell mode.
The traditional DRAM array 100 shown in FIG. 1 can also operate in a differential-cell mode. In the differential-cell mode, two memory cells attached to different bit lines in a column are used to store one bit of binary data. For example, DRAM cell 101 and DRAM cell 102 can be used to store one bit of data in the first column of array 100. Data is written to a column by pulling one of the column bit lines (e.g., BLI) to the VDD supply voltage, and the other one of the column bit lines (e.g., BLI#) to the ground supply voltage. Therefore, in the differential-cell mode, one DRAM cell (e.g., DRAM cell 101) stores a voltage of VDD in the associated capacitor element, and the other DRAM cell (e.g., DRAM cell 102) stores a ground voltage in the associated capacitor element. A differential DRAM cell therefore contains two single DRAM cells that store complementary data. During sensing, word lines connected to both DRAM cells (e.g., WL0 and WL1) are turned on, thereby connecting the cells to the complimentary bit lines. Since the DRAM cells are identically constructed, the coupling between the word lines and the bits lines are equal. As a result, any word line to bit-line coupling noise is cancelled during the differential sensing. Likewise, other coupling noise, such as noise in an N-well in which the DRAM cells are contained, is cancelled. More importantly, the differential signal developed across the complementary bit lines is two times larger than the signal developed across the bit lines during the single-cell mode. As a result, the signal strength of a differential DRAM cell is much stronger and thereby can retain the data much longer. It has been shown that the data retention time in differential-cell mode is greater than the data retention time in single-cell mode by a factor of more than 50. (See, U.S. patent application Ser. No. 10/109,878, by Kurjanowicz et al.)
In power critical applications, such as wireless phones and personal data assistants (PDAs), where the devices operate most of the time in the standby mode, the standby power is critical. For devices that include a DRAM array, the standby power is consumed mainly by refresh operations. It is therefore desirable for the DRAM array to have a long data retention time, such that relatively few refresh operations are required during a given time period. When DRAM array 100 operates in the differential-cell mode, the refresh power is significantly less ( greater than 25 times less) than the refresh power in single-cell mode. That is, even though the power consumed during a refresh operation in the differential-cell mode is relatively high (because two word lines must be turned on for each refresh operation), the overall refresh power is reduced because the number of refresh operations performed in a given period of time is reduced by a factor of greater than 50. Note that in the differential-cell mode, the storage capacity of the DRAM array is reduced by half (because two DRAM cells are used to store one bit of binary data).
U.S. patent application Ser. No. 10/109,878, by Kurjanowicz et al., and U.S. Pat. No. 5,712,823, by Gillingham describe DRAM memory devices that can be operated in either single-cell mode or differential-cell mode. These DRAM memory devices, as a whole or in parts, can be selectively programmed to operate in differential-cell mode or single-cell mode. However, these DRAM devices do not provide means for switching from differential-cell mode to single-cell mode without losing some of the data, as the refresh time and signal levels of the two operating modes are quite different. Likewise, these DRAM devices do not provide means for switching from single-cell mode to differential-cell mode with the data in half of the cells preserved.
It would therefore be desirable to have a memory device that can operate in single-cell mode during normal operation and in differential-cell mode during standby operation. It would further be desirable if up to half of the stored data during normal operation could be preserved when switching from normal operation to standby operation. It would further be desirable if all of the data stored during standby operation could be preserved when switching from standby operation to normal operation.
Accordingly, the present invention provides an array of DRAM cells that are operated in a single-cell mode during normal operating conditions. Upon receiving an asserted standby control signal from an accessing memory client, the array enters a standby mode from the normal operating conditions. The standby mode can be specified as a differential-cell mode, a single-cell mode or a non-retentive mode. To enter the differential-cell standby mode, data stored in the single-cell mode is converted to a differential-cell mode. In this conversion, half of the data stored in the single-cell mode is saved, while the other half is discarded. In the differential-cell standby mode, refresh operations are performed less frequently than in the normal operating mode, thereby conserving power. The external clock signal provided by the accessing memory client can be disabled during the standby mode, as a local clock signal is provided to generate the memory access signals during the standby mode.
In accordance with one embodiment, the conversion from single-cell mode to differential-cell mode is performed as follows. During normal single-cell operation, refresh operations are performed periodically in response to a first refresh enable signal. A standby control signal is asserted, thereby indicating that the standby mode should be entered. The next time the first refresh enable signal is activated, the asserted standby control signal is latched, and a special burst refresh operation is performed.
The special burst refresh operation is implemented as follows. First, an even word line is turned on in accordance with a single-cell read operation. After the data values stored in the memory cells associated with the even word line have developed an adequate signal strength on the bit lines, the sense amplifiers are turned on. The sense amplifiers cause the data signals on the bit lines exhibit a full signal swing. At this time, a corresponding adjacent odd word line is turned on. As a result, the data values stored in single-cell mode DRAM cells associated with the even word line are translated into data values stored in differential-cell mode DRAM cells associated with the even word line and the corresponding odd word line.
During the special burst refresh operation, this process is repeated for all of the rows in the memory array, such that half of the data values stored in the single-cell mode DRAM cells are stored in differential-cell mode DRAM cells, and the other half of the data values stored in the single-cell mode DRAM cells are discarded.
After the special burst refresh operation is complete, the latched standby control signal is stored as a differential-cell mode indicator signal. This differential-cell mode indicator signal causes a second refresh enable signal, having a period much larger than the period of the first refresh enable signal, to control the refresh operations during the differential-cell standby mode. In one embodiment, the period of the second refresh enable signal is about 40 times longer than the period of the first refresh enable signal. In accordance with another embodiment, the periods of the first and second refresh enable signals are automatically adjusted with respect to temperature.
In accordance with another embodiment, the memory array is operated using a clock division scheme, wherein during normal operating conditions, accesses to the memory array are performed while the system clock signal has a first logic state, and refresh operations to the memory array are performed while the system clock signal has a second logic state.
In accordance with yet another embodiment, a plurality of memory blocks that require periodic refresh operate in a single-cell mode during normal operating conditions. Each of these memory blocks can enter a standby mode from the normal operating conditions. A first set of the memory blocks is controlled to operate in first standby mode (e.g., differential-cell mode, single-cell mode or non-retentive mode). A second set of the memory blocks is controlled to operate in a second standby mode, different than the first standby mode. This embodiment advantageously provides flexibility in implementing various standby modes for different memory blocks.
The present invention will be more fully understood in view of the following description and drawings.